JEDEC Solid State Technology Association, a global leader in microelectronics standards, has announced the release of two new standards that bolster support for Compute Express Link (CXL) technology. These additions complete a suite of four comprehensive standards, offering unprecedented flexibility for the development of CXL-based memory products. All four standards are available for free download from JEDEC's website.

JEDEC Expands CXL Support with Two New Standards for Memory Controllers and Device Management-3CGO

JESD319, the JEDEC Memory Controller Standard for CXL, outlines the key specifications for CXL memory controller ASICs. It defines interface parameters, signaling protocols, and critical features, such as CXL interface management, RAS (Reliability, Availability, Serviceability), metadata handling, clocking, and performance configurations. JESD319 focuses on direct-attached memory expansion using CXL 3.1, balancing standardized functionality with room for innovation.

JESD325, the JEDEC Memory Device Management Standard for CXL, provides a reference framework for managing CXL memory devices, particularly those compliant with PCIe Gen 5 and CXL 2.0 or higher. The standard covers management interface requirements, security protocols, thermal management, and field-replaceable unit (FRU) data.

These new standards join JESD317A and JESD405-1B, completing JEDEC’s robust portfolio for CXL memory development. Together, they ensure industry-wide consistency while allowing manufacturers to push boundaries in CXL-based technology.