On September 10, Synopsys announced the release of the world’s first complete 40G UCIe IP solution, designed to meet the increasing performance demands of AI data centers. The UCIe interconnect is critical for efficient chip-to-chip communication in multi-die packages, offering high bandwidth and low latency. This solution enables the seamless transfer of data between heterogeneous and homogeneous chipsets, making it ideal for advanced AI computing systems.
The Synopsys 40G UCIe IP supports both organic substrates and advanced high-density packaging technologies, providing flexibility for developers. This comprehensive solution includes physical layers, controllers, and verification IP, accelerating multi-chip system integration from early design exploration to manufacturing.
Michael Posner, VP of Product Management at Synopsys, emphasized the company's dedication to innovation in semiconductor design, noting their active role in the UCIe Alliance to push forward these standards. Synopsys' solution simplifies IP integration with a single reference clock function, enhanced system reliability through advanced monitoring tools, and broad interoperability with other chip interconnect standards like PCI Express and CXL.
Expected for release in late 2024, the 40G UCIe IP will be compatible with multiple foundries and processes, setting the stage for next-gen multi-chip system designs in AI and high-performance computing.
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